module ALU(
    input [63:0] data1,
    input [63:0] data2,
    input [10:0] ALUControl,

    output reg [63:0] res
);

    always @(*) begin
        case(ALUControl)
            11'b10000000000: begin
                res = data1 + data2;
            end
            11'b01000000000: begin
                res = data1 - data2;
            end
            11'b00100000000: begin //32->64
                res = {data2[31:12], 12'd0};
            end
            11'b00010000000: begin //32->64
                res = data1 + (data2 << 12);
            end
            11'b00001000000: begin
                res = data1 ^ data2;
            end
            11'b00000100000: begin
                res = data1 | data2;
            end
            11'b00000010000: begin
                res = data1 & data2;
            end
            11'b00000001000: begin
                res = (data1 < data2) ? 64'd1 : 64'd0;
            end
            11'b00000000100: begin
                res = data1 << data2;
            end
            11'b00000000010: begin
                res = data1 >> data2;
            end
            11'b00000000001: begin
                res = data1 >>> data2;
            end
            default : begin
                res = 64'd0;
            end
        endcase
    end

endmodule
